发表

A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA

作者：Z. Yuan, B. Yuan, Y. Gu, Y. Zheng, Yunxiang He, X. Wang, C. Rao, P. Zhou, J. Yu, X. Lou

2024 · IEEE Custom Integrated Circuits Conference (CICC) · Neural Rendering Hardware